This new HBM4 memory controller IP not only exceeds current capabilities but is also available for licensing, with early access opportunities for design customers.

JEDEC is finalizing the HBM4 specification, which is expected to double the data lines to 2,048 and potentially achieve 1.6 TB/s bandwidth per device.

The advantages of HBM technology include outstanding bandwidth performance, power efficiency, and space savings, making it particularly suitable for AI applications.

Rambus has launched the industry's first HBM4 controller IP, designed specifically to enhance next-generation AI workloads.

The HBM4 Controller supports a data rate of 6.4 Gbps and can operate up to 10 Gbps, achieving a throughput of 2.56 TB/s per memory device.

Industry leaders, including Cadence and Samsung Electronics, have expressed strong support for the HBM4 technology, recognizing its critical role in AI and high-performance computing applications.

Neeraj Paliwal from Rambus emphasized that the HBM4 Controller IP is vital for overcoming memory bandwidth challenges essential for AI training and inference, particularly as large language models grow beyond a trillion parameters.

Despite the higher manufacturing costs and complexity associated with HBM systems compared to traditional memory architectures, the benefits for AI training are substantial.

The rapid growth of generative AI, driven by large language models exceeding a trillion parameters, is significantly influencing advancements in computing technology.

If HBM4 memory subsystems achieve 10 GT/s, four stacks could provide over 10 TB/s bandwidth, showcasing the potential for enhanced speed and stability.

Rambus is collaborating with companies like Cadence, Samsung, and Siemens to ensure the smooth integration of HBM4 technology into existing systems.

The introduction of HBM3 in 2022 set a precedent by achieving over 3.2 TB/s of bandwidth through four stacks connected to a processor at 6.4 Gb/s.